Data Sheet M10693EJ7V0DS00

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µµµµPD43257B

Write Cycle Timing Chart 2 (/CE1 Controlled)

Data in

High impedance

Address (Input)

/CE1 (Input)

I/O (Input)

High

impedance

CE2 (Input)

/WE (Input)

Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.

2. When I/O pins are in the output state, therefore the input signals must not be applied to

the output.

Remark

Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.

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