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UPD44323362 Datenblatt(PDF) 3 Page - NEC |
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UPD44323362 Datenblatt(HTML) 3 Page - NEC |
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3 / 28 page ![]() 3 Data Sheet M16379EJ4V0DS µµµµPD44323362 Pin Name and Functions Pin name Description Function VDD Core Power Supply Supplies power for RAM core VSS Ground VDDQ Output Power Supply Supplies power for output buffers VREF Input Reference K, /K Main Clock SA0 to SA19 Synchronous Address Input DQa1 to DQd9 Synchronous Data Input / Output /SS Synchronous Chip Select Logically selects SRAM /SW Synchronous Byte Write Enable Write command /SBa Synchronous Byte "a" Write Enable Write DQa1 to DQa9 /SBb Synchronous Byte "b" Write Enable Write DQb1 to DQb9 /SBc Synchronous Byte "c" Write Enable Write DQc1 to DQc9 /SBd Synchronous Byte "d" Write Enable Write DQd1 to DQd9 /G Asynchronous Output Enable Asynchronous input ZZ Asynchronous Sleep Mode Enables sleep mode, active high ZQ Output Impedance Control M1, M2 Mode Select Selects operation mode Note NC No Connection TMS Test Mode Select (JTAG) TDI Test Data Input (JTAG) TCK Test Clock Input (JTAG) TDO Test Data Output (JTAG) Note This device only supports Single Differential Clock, R/R Mode. (R/R stands for Registered Input / Registered Output.) |
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