32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM

1M-WORD BY 36-BIT

HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE

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DATA SHEET

MOS INTEGRATED CIRCUIT

Document No. M16379EJ4V0DS00 (4th edition)

Date Published May 2004 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2002

Description

The

technology using Full-CMOS six-transistor memory cell.

The

bit configuration, such as cache and buffer memory.

The

Features

• Fully synchronous operation

• HSTL Input / Output levels

• Fast clock access time: 2.0 ns / 250 MHz

• Asynchronous output enable control: /G

• Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9)

• Common I/O using three-state outputs

• Internally self-timed write cycle

• Late write with 1 dead cycle between Read-Write

• User-configurable outputs: Controlled impedance outputs or push-pull outputs

• Boundary scan (JTAG) IEEE 1149.1 compatible

• 2.5 ± 0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply

• 119 bump BGA package, 1.27 mm pitch, 14 mm × 22 mm

• Sleep mode: ZZ (Enables sleep mode, active high)

Ordering Information

Part number

Access time

Clock frequency

Package

2.0 ns

250 MHz

119-pin PLASTIC BGA