| Datenblatt-Suchmaschine für elektronische Bauteile |
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80C17 Datenblatt(PDF) 6 Page - TEKTRONIX, INC. |
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80C17 Datenblatt(HTML) 6 Page - TEKTRONIX, INC. |
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6 / 16 page ![]() DSA8300 Record Length 50, 100, 250, 500, 1000, 2000, 4000, 8000, or 16000 samples (magnification views have maximum record length of 4000 samples) Longer Records Available IConnect ®: 1M samples 80SJNB Jitter, Noise, and BER Analysis Software: 10M samples (100k unit intervals, 100 samples per unit interval) Trigger system Trigger Sources Clock Input/Prescale Trigger (front panel) TDR clock (generated internally) Clock recovery triggers from Optical Sampling modules and Electrical Clock Recovery modules (internally connected) Phase Reference (when using the 82A04B Phase Reference module) time base supports acquisitions without a trigger signal in its Free Run mode Trigger Direct Input (front panel) Clock Input / Prescale Trigger Input Clock Input Sensitivity 150 mVp-p to 1 Vp-p, 0.15 GHz to 20 GHz (typical) 200 mVp-p to 1 Vp-p, 0.8 GHz to 15 GHz (guaranteed) Minimum Slew Rate ≥2 V/ns Clock Input Range 1.0 Vp-p (max) – AC coupled Pattern Lengths Supported (for Pattern Triggering with ADVTRIG Option) 2 to 223 (8,388,608) inclusive Clock Input Jitter in Clock-eye and Clock-pattern Trigger Modes (Typical) 0.15 - 0.40 GHz: 900 fs (RMS) 0.40 - 1.25 GHz: 800 fs 1.25 - 20 GHz: 425 fs Clock Input Jitter in Clock-eye and Clock-pattern Trigger Modes (Max) 0.80 - 1.25 GHz: 900 fs (RMS) 1.25 - 11.20 GHz: 500 fs 11.20 - 15.0 GHz: 600 fs TDR Trigger TDR Step Rate Selectable from 25 to 300 kHz in 1 kHz steps Actual TDR step rate may vary up to 2% from requested rate TDR Trigger Jitter 1.3 ps RMS (typical) 1.8 ps RMS (max) Phase Reference Time Base Phase Reference Input Range Standard 82A04B: 8 - 32 GHz (guaranteed), 2 - 32 GHz (typical) 82A04B Option 60G: 8 - 60 GHz (guaranteed), 2 - 70 GHz (typical) For non-sinusoidal clock at frequencies <8 GHz, it may be necessary to filter the clock input to eliminate harmonics from the clock signal (see accessories 020-2566-xx, 020-2567-xx, and 020-2568-xx) Phase Reference Input Sensitivity Best jitter performance is with the clock input to the 82A04B in the following range: 0.6 - 1.8 V. The phase reference time base remains operational to 100 mV (typical) with increased jitter Jitter f ≥8 GHz: 100 fs RMS, on a 10 GHz or faster sampling module 2 GHz ≤ f ≤ 8 GHz: 140 fs RMS, typical on a 10 GHz or faster acquisition module Datasheet Horizontal system 6 www.tek.com |
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