STM32MP153C datasheet(52/254 Pages) STMICROELECTRONICS

52 / 254 page

Functional overview

STM32MP153C/F

52/254

DS12503 Rev 3

3.42

Management data input/output (MDIOS)

The devices embed a MDIO slave interface. It includes the following features:

•

32 MDIO register addresses, each of which is managed using separate input and

output data registers:

–

32 x 16-bit firmware read/write, MDIO read-only output data registers

–

32 x 16-bit firmware read-only, MDIO write-only input data registers

•

Configurable slave (port) address

•

Independently maskable interrupts/events:

–

MDIO register write

–

MDIO register read

–

MDIO protocol error

•

Able to operate in and wake up from Stop mode

3.43

Secure digital input/output MultiMediaCard interface

(SDMMC1, SDMMC2, SDMMC3)

Three secure digital input/output MultiMediaCard interfaces (SDMMC) provide an interface

between the AHB bus and SD memory cards, SDIO cards and MMC devices.

The SDMMC features include the following:

•

Full compliance with MultiMediaCard System Specification Version 4.51.

Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit.

•

Full compatibility with previous versions of MultiMediaCards (backward compatibility).

•

Full compliance with SD memory card specifications version 4.1.

(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and

UHS-II mode not supported).

•

Full compliance with SDIO card specification version 4.0.

Card support for two different databus modes: 1-bit (default) and 4-bit.

(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and

UHS-II mode not supported).

•

Data transfer up to 208 Mbyte/s for the 8-bit mode.

(depending maximum allowed I/O speed).

•

Data and command output enable signals to control external bidirectional drivers.

•

The SDMMC host interface embeds a dedicated DMA controller allowing high-speed

transfers between the interface and the SRAM.

•

IDMA linked list support

Each SDMMC is coupled with a delay block (DLYBSD) allowing support of an external data

frequency above 100 MHz.

3.44

Controller area network (FDCAN1, FDCAN2)

The controller area network (CAN) subsystem consists of two CAN modules, a shared

message RAM memory and a clock calibration unit.

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