STM32MP153C datasheet(21/254 Pages) STMICROELECTRONICS

21 / 254 page

DS12503 Rev 3

21/254

STM32MP153C/F

Functional overview

NEON

NEON technology can accelerate multimedia and signal processing algorithms such as

video encode/decode, 2D/3D graphics, gaming, audio and speech processing, image

processing, telephony, and sound synthesis. The Cortex-A7 provides an engine that offers

both the performance and functionality of the Cortex-A7 floating-point unit (FPU) and an

implementation of the NEON advanced SIMD instruction set for further acceleration of

media and signal processing functions. The NEON extends the Cortex-A7 processor FPU to

provide a quad-MAC and additional 64-bit and 128-bit register set supporting a rich set of

SIMD operations over 8-, 16- and 32-bit integer and 32-bit floating-point data quantities.

Hardware virtualization

Highly efficient hardware support for data management and arbitration, whereby multiple

software environments and their applications are able to simultaneously access the system

capabilities. This enables the realization of devices that are robust, with virtual environments

that are well isolated from each other.

Optimized L1 caches

Performance and power optimized L1 caches combine minimal access latency techniques

to maximize performance and minimize power consumption. There is also the option of

cache coherence for enhanced inter-processor communication, or support of a rich SMP

capable OS for simplified multicore software development.

Integrated L2 cache controller

Provides low-latency and high-bandwidth access to cached memory in high-frequency, or to

reduce the power consumption associated with off-chip memory access.

Cortex-A7 floating-point unit (FPU)

The FPU provides high-performance single and double precision floating-point instructions

compatible with the Arm VFPv4 architecture that is software compatible with previous

generations of Arm floating-point coprocessor.

Snoop control unit (SCU)

The SCU is responsible for managing the interconnect, arbitration, communication, cache to

cache and system memory transfers, cache coherence and other capabilities for the

processor.

This system coherence also reduces software complexity involved in maintaining software

coherence within each OS driver.

Generic interrupt controller (GIC)

Implementing the standardized and architected interrupt controller, the GIC provides a rich

and flexible approach to inter-processor communication and the routing and prioritization of

system interrupts.

Supporting up to 288 independent interrupts, under software control, each interrupt can be

distributed across A7 cores, hardware prioritized, and routed between the operating system

and TrustZone software management layer.

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