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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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KSZ8893FQL Datenblatt(PDF) 1 Page - Microchip Technology |
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KSZ8893FQL Datenblatt(HTML) 1 Page - Microchip Technology |
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1 / 109 page  2019 Microchip Technology Inc. DS00003038B-page 1 Features • Integrated 3-Port 10/100 Ethernet Switch - Three MACs and Two PHYs Fully Compliant with IEEE 802.3u Standard - Non-Blocking Switch Fabric Ensures Fast Packet Delivery by Utilizing an 1K MAC Address Lookup Table and a Store-and-Forward Architecture - Full-Duplex IEEE 802.3x Flow Control (PAUSE) with Force Mode Option - Half-Duplex Back Pressure Flow Control - HP Auto MDI-X for Reliable Detection of and Correction for Straight-Through and Crossover Cables with Disable and Enable Option - Microchip LINKMD® TDR-Based Cable Diag- nostics Permit Identification of Faulty Copper Cabling - 100BASE-FX, 100BASE-SX, and 10BASE-FL Fiber Support on Port 1 - MII Interface Supports Both MAC Mode and PHY Mode - RMII Interface Support with External 50 MHz System Clock - 7-Wire Serial Network Interface (SNI) Support for Legacy MAC - Comprehensive LED Indicator Support for Link, Activity, Full-/Half-Duplex and 10/100 Speed • Fiber Support - Integrated LED Driver and Post Amplifier for 10BASE-FL and 100BASE-SX Optical Modules • TTC TS-1000 OAM - Supports OAM Sub-Layer which Conforms to TS-1000 V2 Specification from Telecommunica- tion Technology Committee (TTC) - Sends and Receives OAM Frames to Center or Terminal Side - Loopback Mode to Support Loopback Packet from Center Side to Terminal Side - Far-End Fault Detection with Disable and Enable - Link Transparency to Indicate Link Down from Link Partner - Unique User Defined Register (UDR) Feature Brings OAM to Low Cost/Complexity Nodes • Comprehensive Configuration Register Access - SMI, SPI, and I2C Management Interfaces to All 8-bit Internal Registers - MII Management (MIIM) Interface to PHY Reg- isters - I/O Pins Strapping and EEPROM to Program Selective Registers in Unmanaged Switch Mode - Control Registers Configurable on the Fly (Port- Priority, 802.1p/d/q, AN…) • QoS/CoS Packet Prioritization Support - Per Port, 802.1p, and DiffServ-Based - Re-Mapping of 802.1p Priority Field Per Port Basis - Four Priority Levels • Advanced Switch Features - IEEE 802.1q VLAN Support for Up to 16 Groups (Full Range of VLAN IDs) - VLAN ID Tag/Untag Options, Per Port Basis - IEEE 802.1p/q Tag Insertion or Removal on a Per Port Basis (Egress) - Programmable Rate Limiting at the Ingress and Egress on a Per Port Basis - Broadcast Storm Protection with Percent Con- trol (Global and Per Port Basis) - IEEE 802.1d Spanning Tree Protocol Support - Special Tagging Mode to Inform the Processor which Ingress Port Receives the Packet - IGMP Snooping (IPv4) and MLD Snooping (IPv6) Support for Multicast Packet Filtering - MAC Filtering Function to Forward Unknown Unicast Packets to Specified Port - Double-Tagging Support • Low Latency Support - Repeater Mode • Switch Monitoring Features - Port Mirroring/Monitoring/Sniffing: Ingress and/ or Egress Traffic to Any Port or MII - MIB Counters for Fully Compliant Statistics Gathering, 34 MIB Counters Per Port - Loopback Modes for Remote Diagnostic of Fail- ure • Low Power Dissipation - Full-Chip Hardware Power-Down (Register Configuration Not Saved) - Per Port Based Software Power-Save on PHY (Idle Link Detection, Register Configuration Pre- served) - Voltages: Core 1.2V, I/O and Transceiver 3.3V • Available in a 128-Pin PQFP, Lead-Free Package Applications • Media Conversion Modules - 10BASE-FL to/from 10BASE-T - 100BASE-SX to/from 100BASE-TX - 100BASE-FX to/from 100BASE-TX • FTTx Managed/Unmanaged Media Converters • Fiber Broadband Gateways KSZ8893FQL Single-Chip 3-Port Switch with Fiber Support |
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