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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADC32RF83 Datenblatt(PDF) 97 Page - Texas Instruments |
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ADC32RF83 Datenblatt(HTML) 97 Page - Texas Instruments |
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97 / 138 page  97 ADC32RF80, ADC32RF83 www.ti.com SBAS774A – MAY 2016 – REVISED DECEMBER 2016 Product Folder Links: ADC32RF80 ADC32RF83 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.5.11.13 Register 03Eh (address = 03Eh), JESD Digital Page Figure 186. Register 03Eh 7 6 5 4 3 2 1 0 0 MASK CLKDIV SYSREF MASK NCO SYSREF 0 0 0 0 0 W-0h R/W-0h R/W-0h W-0h W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 71. Register 03Eh Field Descriptions Bit Field Type Reset Description 7 0 W 0h Must write 0 6 MASK CLKDIV SYSREF R/W 0h Use this bit to mask the SYSREF going to the input clock divider. 0 = Input clock divider is reset when SYSREF is asserted (that is, when SYSREF transitions from low to high) 1 = Input clock divider ignores SYSREF assertions 5 MASK NCO SYSREF R/W 0h Use this bit to mask the SYSREF going to the NCO in the DDC block and LMFC counter of the JESD interface. 0 = NCO phase and LMFC counter are reset when SYSREF is asserted (that is, when SYSREF transitions from low to high) 1 = NCO and LMFC counter ignore SYSREF assertions 4-0 0 W 0h Must write 0 8.5.12 Decimation Filter Page Direct Addressing, 16-Bit Address, 5000h for Channel A, 5800h for Channel B 8.5.12.1 Register 000h (address = 000h), Decimation Filter Page Figure 187. Register 000h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DDC EN W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 72. Register 000h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 0 DDC EN R/W 0h This bit enables the decimation filter and disables the bypass mode. 0 = Do not use 1 = Decimation filter enabled |
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