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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADC32RF83 Datenblatt(PDF) 104 Page - Texas Instruments |
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ADC32RF83 Datenblatt(HTML) 104 Page - Texas Instruments |
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104 / 138 page  104 ADC32RF80, ADC32RF83 SBAS774A – MAY 2016 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF80 ADC32RF83 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.5.12.18 Register 016h (address = 016h), Decimation Filter Page Figure 204. Register 016h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DDC1 6DB GAIN W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 89. Register 016h Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 0 DDC1 6DB GAIN R/W 0h This bit scales the output of DDC1 by 2 (6 dB) to compensate for real-to-complex conversion and image suppression. This scaling does not apply to the high-bandwidth filter path (divide- by-4 and -6); see register 1Fh. 0 = Normal operation 1 = 6-dB digital gain is added 8.5.12.19 Register 01Eh (address = 01Eh), Decimation Filter Page Figure 205. Register 01Eh 7 6 5 4 3 2 1 0 0 DDC DET LAT 0 0 0 0 W-0h R/W-0h W-0h W-0h W-0h W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 90. Register 01Eh Field Descriptions Bit Field Type Reset Description 7 0 W 0h Must write 0 6-4 DDC DET LAT R/W 0h These bits ensure deterministic latency depending on the decimation setting used; see Table 91. 3-0 0 W 0h Must write 0 Table 91. DDC DET LAT Bit Settings SETTING COMPLEX DECIMATION SETTING 10h Divide-by-24, -32 complex 20h Divide-by-16, -18, -20 complex 40h Divide-by-by 6, -12 complex 50h Divide-by-4, -8, -9, -10 complex |
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