ADC32RF83 datasheet(109/138 Pages) TI

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109

ADC32RF80, ADC32RF83

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SBAS774A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: ADC32RF80 ADC32RF83

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8.5.13 Power Detector Page

8.5.13.1 Register 000h (address = 000h), Power Detector Page

Figure 215. Register 000h

PKDET EN

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 98. Register 000h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Must write 0

PKDET EN

R/W

This bit enables the peak power and crossing detector.

0 = Power detector disabled

1 = Power detector enabled

8.5.13.2 Register 001h-002h (address = 001h-002h), Power Detector Page

Figure 216. Register 001h

BLKPKDET [7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 217. Register 002h

BLKPKDET [15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 99. Register 001h-002h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

BLKPKDET

R/W

This register specifies the block length in terms of number of

samples (S`) used for peak power computation. Each sample S`

is a peak of 8 actual ADC samples. This parameter is a 17-bit

value directly in linear scale. In decimation mode, the block

length must be a multiple of a divide-by-4 or -6 complex: length

= 5 × decimation factor.

The divide-by-8 to -32 complex: length = 10 × decimation factor.

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