September 2005

ASM5P2308A

rev 1.4

3.3V Zero Delay Buffer

2 of 18

Notice: The information in this document is subject to change without notice.

Block Diagram

Select Input Decoding for ASM5P2308A

S2

S1

Clock A1 - A4

Clock B1 - B4

Output Source

PLL Shut-Down

0

0

Three-state

Three-state

PLL

Y

0

1

Driven

Three-state

PLL

N

1

0

Driven

1

Driven

Reference

Y

1

1

Driven

Driven

PLL

N

ASM5P2308A Configurations

Device

Feedback From

Bank A Frequency

Bank B Frequency

ASM5P2308A-1

Bank A or Bank B

Reference

Reference

ASM5P2308A-1H

Bank A or Bank B

Reference

Reference

ASM5P2308A-2

Bank A

Reference

Reference /2

ASM5P2308A-2

Bank B

2 X Reference

Reference

ASM5P2308A-3

Bank A

2 X Reference

Reference or Reference

2

ASM5P2308A-3

Bank B

4 X Reference

2 X Reference

ASM5P2308A-4

Bank A or Bank B

2 X Reference

2 X Reference

ASM5P2308A-5H

Bank A or Bank B

Reference /2

Reference /2

Note:

1. Outputs are non- inverted on ASM5P2308A-2 and ASM5P2308A-3 in bypass mode, S2 = 1 and S1 = 0.

2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P2308A-2.

/2

MUX

Select Input

Decoding

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (-2, -3)

PLL

/2

/2

Extra Divider (-3, -4)

Extra Divider (-5H)

REF

S2

S1

FBK

ASM5P2308A