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TLV9152SIRUGR Datenblatt(PDF) 5 Page - Texas Instruments |
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TLV9152SIRUGR Datenblatt(HTML) 5 Page - Texas Instruments |
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5 / 63 page ![]() 1 OUT1 8 V+ 2 IN1± 7 OUT2 3 IN1+ 6 IN2± 4 V± 5 IN2+ Not to scale Thermal Pad 1 OUT1 8 V+ 2 IN1± 7 OUT2 3 IN1+ 6 IN2± 4 V± 5 IN2+ Not to scale 5 TLV9151, TLV9152, TLV9154 www.ti.com SBOS986B – OCTOBER 2019 – REVISED MAY 2020 Product Folder Links: TLV9151 TLV9152 TLV9154 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated TLV9152 D, DDF, DGK, and PW Package(1) 8-Pin SOIC, SOT-23-8, TSSOP, and VSSOP Top View (1) DDF and DGK packages are preview only. TLV9152 DSG Package(1) 8-Pin WSON With Exposed Thermal Pad Top View (1) Connect thermal pad to V–. See Packages With an Exposed Thermal Pad section for more information. Pin Functions: TLV9152 PIN I/O DESCRIPTION NAME SOIC, SOT-23-8, TSSOP, VSSOP, WSON +IN A 3 I Noninverting input, channel A +IN B 5 I Noninverting input, channel B –IN A 2 I Inverting input, channel A –IN B 6 I Inverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V+ 8 — Positive (highest) power supply V– 4 — Negative (lowest) power supply |
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