ADF4401ABCEZ datasheet(13/39 Pages) AD

13 / 39 page

Data Sheet

ADF4401A

Rev. 0 | Page 13 of 39

THEORY OF OPERATION

PFD

MIXER

LO_IN

RF OUTPUT

VTUNE

REF_PFD

CPOUT

IFOUT

ADF4401A

REFP, REFN

AMP

LPF

HPF

LPF

VCO

CALIBRATION

RF8P, RF8N

÷1, 2, 4, 8,

16, 32, 64

Figure 23. ADF4401A Translation Loop Block Diagram

The ADF4401A is an SiP translation loop (offset loop) module

that includes the VCO and calibration PLL circuit, a

downconversion mixer, and RF and IF amplifiers. This SiP

translates the lower REF_PFD frequency of the external PFD up to

a higher frequency range of 4 GHz to 8 GHz, as determined by

the LO_IN pin.

The phase noise in a PLL circuit can be described as having two

components: a flat noise component known as the PLL noise floor

and a 1/f noise profile component known as the PLL 1/f noise.

A PLL circuit with a low N divider value allows the user to

design a frequency synthesizer with correspondingly low phase

noise performance. See the RF N Divider section for more

information.

The translation loop synthesizer decouples the required channel

spacing from the N divider value to optimize the phase noise of

the PLL. In this translation loop synthesizer circuit, N = 1 is used.

As shown in Figure 23, the ADF4401A locks the higher RF

output frequency range of 4 GHz to 8 GHz to the REF_PFD

frequency of the external PFD. The integrated mixer and the

LO_IN pin perform the divider function of this PLL circuit.

The integrated RF amplifiers provide the required LO isolation,

and the IF amplifiers provide the required external IFOUT levels.

With the LO in the feedback loop, the equation at the external

PFD is as follows for high-side injection (IF = LO − RF):

REF_PFD/R = (LO_IN − RF8x)/N

where:

R is the R divider.

N is the N divider.

For low-side injection (IF = RF − LO),

REF_PFD/R = (RF8x − LO_IN)/N

In this circuit, R and N = 1. Thus, the output frequency is

RF8x = LO_IN ± REF_PFD.

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