ADF4401ABCEZ datasheet(21/39 Pages) AD

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Data Sheet

ADF4401A

Rev. 0 | Page 21 of 39

EXTERNAL PHASE DETECTOR

To take advantage of the ability of the architecture of offset

loop PLLs to generate extremely low noise carrier frequencies,

it is important to use a phase detector or PFD that can operate

at high frequencies, minimizing the need for any dividers that

can degrade the in band noise response.

The 1.3 GHz phase comparison frequency of the HMC3716

makes it ideal for use with the IF range of the ADF4401A. The

ability of such a circuit to compare both frequency and phase

means no additional circuitry is required to steer the frequency

to the intended output frequency.

Mixers can also be used as phase detectors, but these require

additional circuitry to steer the frequency within the capture

range of the mixer (the intended frequency ± the external loop

bandwidth).

PHASE DETECTOR REFERENCE

In addition to choosing a low noise LO source and high frequency

low noise phase detector, the reference frequency to the external

phase detector is also of critical importance. For most applications,

the external phase detector reference must have fast switching

and high resolution. For this reason, direct digital synthesizers

(DDSs) are highly recommended. A devices like the AD9162 is

suitable and cover the IF range of the ADF4401A.

POWER SUPPLIES

To ensure optimal performance, connect a low noise regulator,

such as the ADM7150, to all supply pins.

PCB DESIGN GUIDELINES

Connect all of the GND pins to as large a copper pour or plane

area as possible on the top layer. Avoid breaking the ground

connection between the external components and the ADF4401A.

For optimal heatsinking, use vias to connect the GND copper

area to the internal ground planes of the PCB. Liberally

distribute these GND vias to provide both an optimal ground

connection and thermal path to the internal planes of the PCB.

Pay attention to the location and density of the thermal vias.

The ADF4401A can benefit from the heatsinking afforded by

vias that connect to internal GND planes at these locations due

to their proximity to internal power handling components. The

optimum number of thermal vias depends on the PCB design.

For example, a PCB may use small via holes and therefore must

employ more thermal vias than a board that uses larger holes.

For a microwave PLL and VCO synthesizer, such as the

ADF4401A, care must be taken with the board stackup and

layout. Do not use FR4 material because it can cause signal

power loss above 3 GHz. Instead, the Rogers 4350, Rogers 4003,

or Rogers 3003 dielectric material is suitable.

Care must be taken with the RF output traces to minimize

discontinuities and ensure optimal signal integrity. Via placement

and grounding are critical.

OUTPUT MATCHING

The RF8P and RF8N pins can be ac-coupled to the next circuit,

if desired. However, if higher output power is required, use a

pull-up inductor to VRF_OUT to increase the output power

level as shown in Figure 34.

7.5nH

10pF

RF8P

VRF_OUT

Ω

Figure 34. Optimum Output Stage

When differential outputs are not needed, terminate the

unused output or combine the outputs using a balun.

For frequencies below 2 GHz, use a 100 nH inductor instead of

a 7.5 nH inductor on the RF8P and RF8N pins.

The RF8P and RF8N pins are a differential circuit. Provide each

output with the same (or similar) components where possible,

such as a similar shunt inductor value, bypass capacitor, and

termination.

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