LP5860 datasheet(46/57 Pages) TI

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Table 9-1. Design Parameters (continued)

PARAMETER

VALUE

LED maximum peak current (red, green, blue)

44 mA, 33 mA, 22 mA

9.2.3 Detailed Design Procedure

LP5860 requires an external capacitor CVCAP, whose value is 1 μF connected from VCAP to GND for proper

operation of internal LDO. It should be placed as close to the device as possible.

1-μF capacitors are recommended to be placed between VCC / VLED with GND, and 1 nF capacitor placed

between VIO with GND. Place the capacitors as close to the device as possible.

Pull-up resistors Rpull-up are requirement for SCL and SDA when using I2C as communication method. In typical

applications, 1.8-kΩ to 4.7-kΩ resistors are recommended.

To decrease thermal dissipation from device to ambient, resistors RCS could optionally be placed in serial with

the LED. Voltage drop on these resistors should left enough margins for VSAT to ensure the device work

normally.

9.2.4 Program Procedure

When selecting data refresh Mode 1, outputs are refreshed instantly once data is received.

When selecting data refresh Mode 2/3, VSYNC signal is required for synchronized display. Programming flow is

showed as Figure 9-2. To display full pixel of last frame, VSYNC pulse should be sent to the device after the

end of last PWM. Time between two pulses tSYNC should be larger than the whole PWM time of all Dots tframe.

Common selection like 60 Hz, 90 Hz, 120 Hz or even higher refresh frequency could be supported. High pulse

width longer than tSYNC_H is required at the beginning of each VSYNC frame, and data should not be write to

PWM registers during high pulse width.

Power up VCC /

VIO / VLED

Config initialization

registers

Write frame data

Send VSYNC pulse

Write frame data of

next frame

Update frame?

Figure 9-2. Program Procedure

LP5860

SNVSBU8 – MAY 2021

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