CY24239PVC datasheet(6/15 Pages) CYPRESS

6 / 15 page

CY24239

Document #: 38-07038 Rev. **

Page 6 of 15

Writing Data Bytes

Each bit in Data Bytes 0–7 controls a particular device function

except for the “reserved” bits which must be written as a logic

0. Bits are written MSB (most significant bit) first, which is bit 7.

Table 5 gives the bit formats for registers located in Data Bytes

0–7.

Table 6 details additional frequency selections that are avail-

able through the serial data interface.

Table 7 details the select functions for Byte 0, bits 1 and 0.

Table 5. Data Bytes 0–7 Serial Configuration Map

Bit(s)

Affected Pin

Control Function

Bit Control

Default

Pin No.

Pin Name

Data Byte 0

(Reserved)

SEL2

Refer to Table 6

SEL1

Refer to Table 6

SEL0

Refer to Table 6

Frequency Table Selection

Frequency Con-

trolled by FS(3:0) Ta-

ble 2

Frequency Con-

trolled by SEL(3:0)

Table 6

SEL3

Refer to Table 6

(Reserved)

Test Mode

Normal

Three-stated

Data Byte 1

7--

6--

5--

4--

SDRAM16

Clock Output Disable

LOW

Active

CPU2

Clock Output Disable

LOW

Active

CPU1

Clock Output Disable

LOW

Active

CPU_F

Clock Output Disable

LOW

Active

Data Byte 2

(Reserved)

PCI_F

Clock Output Disable

LOW

Active

PCI5

Clock Output Disable

LOW

Active

PCI4

Clock Output Disable

LOW

Active

PCI3

Clock Output Disable

LOW

Active

PCI2

Clock Output Disable

LOW

Active

PCI1

Clock Output Disable

LOW

Active

PCI0

Clock Output Disable

LOW

Active

Data Byte 3

(Reserved)

48MHz

Clock Output Disable

LOW

Active

24MHz

Clock Output Disable

LOW

Active

33, 32,

25, 24

SDRAM12:15

Clock Output Disable

LOW

Active

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