CY24239
Document #: 38-07038 Rev. **
Page 12 of 15
SDRAM 0:16 Clock Outputs (Lump Capacitance Test Load = 22 pF)
Parameter
Description
Test Condition/
Comments
SDRAMIN =
100 MHz
Unit
Min.
Typ.
Max.
tP
Period
Measured on rising edge at 1.5V
10
10.5
ns
tH
High Time
Duration of clock cycle above 2.4V
3.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
2.0
ns
tR
Output Rise Edge
Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge
Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.5V
45
55
%
tSK
Output Skew
Measured on rising and falling edge at
1.5V
250
ps
tPD
Propagation
Delay
Measured from SDRAMIN
3.7
ns
Zo
AC Output
Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
15
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
fD
Deviation from 48 MHz
(48.008 – 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
25
Ω
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