ACE25QA200G

2M BIT SPI NOR FLASH

VER 1.2

13

Dual Output Fast Read (3BH)

See Figure 7, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy

byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit

per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data is shifted out

ID and Security Instructions

Read Manufacture ID/ Device ID (90H)

See Figure 8, the Read Manufacturer/Device ID instruction is an alternative to the Release from

Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific

Device ID.

The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H” followed by a

24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be

read first.

Figure 7. Dual Output Fast Read Sequence Diagram

Figure 8. Read Manufacture ID/ Device ID Sequence Diagram