ACE25QA200G

2M BIT SPI NOR FLASH

VER 1.2

7

SRP bits

The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The

Status Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the Hardware

Protected mode. When the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven

Low. In this mode, the non-volatile bits of the Status Register (SRP, BP2, BP1, and BP0) become read-only

bits and the Write Status Register (WRSR) instruction is not execution. The default value of SRP is 0.

Write Protect Features

(A)

Software Protection: The Block Protect (BP2, BP1, and BP0) bits define the section of the memory

array that can be read but not change.

(B)

Hardware Protection: /WP going low to protected the BP0~BP2 bits and SRP bits.

(C)

Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the Release from

deep Power-Down Mode instruction.

(D)

Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program, Sector Erase,

Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction.