33

AT25DF256

DS-25DF256–035D–2/2017

14.

Power-On/Reset State

When power is first applied to the device, or when recovering from a reset condition, the output pin (SO) will be in a high

impedance state, and a high-to-low transition on the CSB pin will be required to start a valid instruction. The SPI mode

(Mode 3 or Mode 0) will be automatically selected on every falling edge of CSB by sampling the inactive clock state.

14.1 Power-Up/Power-Down Voltage and Timing Requirements

are disabled and the device will not respond to any commands.

If the first operation to the device after power-up will be a program or erase operation, then the operation cannot be

mode if CSB is at logic low. For the case of Power-down then Power-up operation, or if a power interruption occurs (such

Table 14-1. Voltage and Timing Requirements for Power-Up/Power-Down

Figure 14-1. Power-Up Timing

Symbol

Parameter

Min

Max

Units

(1)

1.

Not 100% tested (value guaranteed by design and characterization).

1.0

V

(1)

Minimum duration for device initialization

300

µs

70

µs

(1)

1

500000

µs/V

Power on reset voltage

1.45

1.6

V

Power up delay time before Program or Erase is allowed

3

ms

VCC

V

Max V

PWD

Time

t

PWD

t

PUW

Full Operation Permitted

t

VR

t

VCSL

Read Operation

Permitted