PCIMX6DP5AVT2AB datasheet(63/166 Pages) NXP

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Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018

NXP Semiconductors

WE40

EIM_LBA_B Invalid to

EIM_CSx_B Invalid (ADVL is

asserted)

WE7-WE15-CSN

×t-3.5-CSN×t3.5-CSN×tns

WE40A

(muxed

A/D)

EIM_CSx_B Valid to EIM_LBA_B

Invalid

WE14-WE6+(ADVN+ADVA+1-

CSA)

×t

-3.5+(ADVN+AD

VA+1-CSA)

×t

3.5+(ADVN+ADVA

+1-CSA)

×t

WE41

EIM_CSx_B Valid to Output Data

Valid

WE16-WE6-WCSA

×t-3.5-WCSA×t3.5-WCSA×tns

WE41A

(muxed

A/D)

EIM_CSx_B Valid to Output Data

Valid

WE16-WE6+(WADVN+WADVA

+ADH+1-WCSA)

×t

-3.5+(WADVN+

WADVA

+ADH+1-WCSA)

×t

3.5+(WADVN+WADVA

+ADH+1-WCSA)

×t

WE42

Output Data Invalid to EIM_CSx_B

Invalid

WE17-WE7-CSN

×t-3.5-CSN×t3.5-CSN×tns

MAXCO Output maximum delay from

internal driving

EIM_ADDRxx/control flip-flops to

chip outputs.

—

MAXCSO Output maximum delay from

internal chip selects driving

flip-flops to EIM_CSx_B out.

—

MAXDI EIM_DATAxx MAXIMUM delay

from chip input data to its internal

flip-flop

5—

WE43

Input Data Valid to EIM_CSx_B

Invalid

MAXCO-MAXCSO+MAXDI

MAXCO-MAXCS

O+MAXDI

—ns

WE44

EIM_CSx_B Invalid to Input Data

Invalid

—

WE45

EIM_CSx_B Valid to EIM_EBx_B

Valid (Write access)

WE12-WE6+(WBEA-WCSA)

×t -3.5+(WBEA-WC

SA)

×t

3.5+(WBEA-WCSA)

×tns

WE46

EIM_EBx_B Invalid to

EIM_CSx_B Invalid (Write access)

WE7-WE13+(WBEN-WCSN)

×t -3.5+(WBEN-WC

SN)

×t

3.5+(WBEN-WCSN)

×tns

MAXDTI Maximum delay from

EIM_DTACK_B input to its internal

flip-flop + 2 cycles for

synchronization

—

WE47

EIM_DTACK_B Active to

EIM_CSx_B Invalid

MAXCO-MAXCSO+MAXDTI

MAXCO-MAXCS

O+MAXDTI

—ns

WE48

EIM_CSx_B Invalid to

EIM_DTACK_B invalid

—

1 For more information on configuration parameters mentioned in this table, see the i.MX 6DualPlus/6QuadPlus reference manual

(IMX6DQPRM).

Table 42. EIM Asynchronous Timing Parameters Relative to Chip Select1, 2 (continued)

Ref No.

Parameter

Determination by Synchronous

measured parameters

Min

Max

Unit

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