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PCIMX6DP5AVT2AB Datenblatt(PDF) 76 Page - NXP Semiconductors |
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PCIMX6DP5AVT2AB Datenblatt(HTML) 76 Page - NXP Semiconductors |
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76 / 166 page ![]() i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018 76 NXP Semiconductors Electrical Characteristics 4.12.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 49 shows the interface timing values. The number field in the table refers to timing signals found in Figure 37 and Figure 38. Table 49. Enhanced Serial Audio Interface (ESAI) Timing ID Parameter1,2 Symbol Expression2 Min Max Condition3 Unit 62 Clock cycle4 tSSICC 4 × Tc 4 × Tc 30.0 30.0 — — i ck i ck ns 63 Clock high period: • For internal clock • For external clock — — 2 × Tc − 9.0 2 × Tc 6 15 — — — — ns 64 Clock low period: • For internal clock • For external clock — — 2 × Tc − 9.0 2 × Tc 6 15 — — — — ns 65 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high — — — — — — 19.0 7.0 x ck i ck a ns 66 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low — — — — — — 19.0 7.0 x ck i ck a ns 67 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) high5 — — — — — — 19.0 9.0 x ck i ck a ns 68 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low5 — — — — — — 19.0 9.0 x ck i ck a ns 69 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high — — — — — — 19.0 6.0 x ck i ck a ns 70 ESAI_RX_CLK rising edge to ESAI_RX_FSout (wl) low — — — — — — 17.0 7.0 x ck i ck a ns 71 Data in setup time before ESAI_RX_CLK (serial clock in synchronous mode) falling edge — — — — 12.0 19.0 — — x ck i ck ns 72 Data in hold time after ESAI_RX_CLK falling edge — — — — 3.5 9.0 — — x ck i ck ns 73 ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK falling edge5 — — — — 2.0 19.0 — — x ck i ck a ns 74 ESAI_RX_FS input (wl) high before ESAI_RX_CLK falling edge — — — — 2.0 19.0 — — x ck i ck a ns 75 ESAI_RX_FS input hold time after ESAI_RX_CLK falling edge — — — — 2.5 8.5 — — x ck i ck a ns 78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high — — — — — — 19.0 8.0 x ck i ck ns 79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low — — — — — — 20.0 10.0 x ck i ck ns 80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) high5 — — — — — — 20.0 10.0 x ck i ck ns |
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