PCIMX6QP4AVT2AB datasheet(34/166 Pages) NXP

34 / 166 page

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018

NXP Semiconductors

Electrical Characteristics

power consumption. If boundary scan test is used, SATA_VP and SATA_VPH must remain

powered.

•

When the PCIE interface is not used, the PCIE_VP, PCIE_VPH, and PCIE_VPTX supplies should

be grounded. The input and output supplies for rest of the ports (PCIE_REXT, PCIE_RX_N,

PCIE_RX_P, PCIE_TX_N, and PCIE_TX_P) can remain unconnected. It is recommended not to

turn the PCIE_VPH supply OFF while the PCIE_VP supply is ON, as it may lead to excessive

power consumption. If boundary scan test is used, PCIE_VP, PCIE_VPH, and PCIE_VPTX must

remain powered.

4.3

Integrated LDO Voltage Regulator Parameters

Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins

named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use

only and should not be used to power any external circuitry. See the i.MX 6DualPlus/6QuadPlus reference

manual (IMX6DQPRM) for details on the power tree scheme recommended operation.

NOTE

The *_CAP signals should not be powered externally. These signals are

intended for internal LDO or LDO bypass operation only.

4.3.1

Digital Regulators (LDO_ARM, LDO_PU, LDO_SOC)

There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because

of their construction). The advantages of the regulators are to reduce the input supply variation because of

their input supply ripple rejection and their on die trimming. This translates into more voltage for the die

producing higher operating frequencies. These regulators have three basic modes.

•

Bypass. The regulation FET is switched fully on passing the external voltage, DCDC_LOW, to the

load unaltered. The analog part of the regulator is powered down in this state, removing any loss

other than the IR drop through the power grid and FET.

•

Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.

The analog part of the regulator is powered down here limiting the power consumption.

•

Analog regulation mode. The regulation FET is controlled such that the output voltage of the

regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV

steps.

Optionally LDO_SOC/VDD_SOC_CAP can be used to power the HDMI, PCIe, and SATA PHY's through

external connections.

For additional information, see the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM).

4.3.2

Regulators for Analog Modules

4.3.2.1

LDO_1P1 / NVCC_PLL_OUT

The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see

Table 6 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V

PCIMX6QP4AVT2AB Datenblatt(PDF) 34 Page - NXP Semiconductors

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