ICS1893BFILF datasheet(78/133 Pages) ICST

78 / 133 page

ICS1893BF, Rev. C, 9/29/05

September, 2005

Chapter 7 Management Register Set

ICS1893BF Data Sheet - Release

7.11.7 Invalid Error Code Test (bit 16.2)

The Invalid Error Code Test bit allows an STA to force the ICS1893BF to transmit symbols that are typically

classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the

serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC

4B/5B definition.

When this bit is logic:

• Zero, the ISO/IEC defined 4B/5B translation takes place.

• One – and the TXER signal is asserted by the MAC – the MII input nibbles are translated according to

Table 7-17.

7.11.8 ICS Reserved (bit 16.1)

See Section 7.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.

7.11.9 Stream Cipher Disable (bit 16.0)

The Stream Cipher Disable bit allows an STA to control whether the ICS1893BF employs the Stream

Cipher Scrambler in the transmit and receive data paths. When this bit is set to logic:

• Zero, the Stream Cipher Encoder and Decoder are both enabled for normal operations.

• One, the Stream Cipher Encoder and Decoder are disabled. This action results in an unscrambled data

stream (for example, the ICS1893BF transmits unscrambled IDLES, and so forth.

Note: The Stream Cipher Scrambler can be used only for 100-MHz operations.

Table 7-17. Invalid Error Code Translation Table

Symbol

Meaning

MII Input

Nibble

Translation

Invalid Code

0000

00000

Invalid Code

0001

00001

Invalid Code

0010

00010

Invalid Code

0011

00011

Error

0100

00100

Invalid Code

0101

00101

Invalid Code

0110

00110

ESD

0111

00111

Invalid Code

1000

00000

ESD

1001

01101

Invalid Code

1010

01100

SSD

1011

10001

Invalid Code

1100

10000

V (S)

Invalid Code

1101

11001

SSD

1110

11000

Idle

1111

11111

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