P87LPC779 datasheet(6/74 Pages) PHILIPS

6 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

6 of 74

9397 750 13213

P1.0 - P1.7

12-8, 4, 3,

I/O

Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable output type, except for three

pins as noted below. Port 1 latches are conﬁgured in the quasi-bidirectional mode and

have either ones or zeros written to them during reset, as determined by the PRHI bit in

the UCFG1 configuration byte. The operation of the configurable port 1 pins as inputs

and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable

port pins are programmed independently. Refer to Section 8.9 “I/O ports” and Table 55

“DC electrical characteristics” for details.

Port 1 also provides various special functions as described below:

P1.0

TxD — Transmitter output for the serial port.

P1.1

RxD — Receiver input for the serial port.

P1.2

I/O

T0 — Timer/counter 0 external count input or overﬂow output.

I/O

SCL — I2C-bus serial clock input/output. When conﬁgured as an output, P1.2 is open

drain, in order to conform to I2C-bus speciﬁcations.

P1.3

INT0 — External interrupt 0 input.

I/O

SDA — I2C-bus serial data input/output. When conﬁgured as an output, P1.3 is open

drain, in order to conform to I2C-bus speciﬁcations.

P1.4

INT1 — External interrupt 1 input.

P1.5

RST — External Reset input (if selected via EPROM conﬁguration). A LOW on this pin

resets the microcontroller, causing I/O ports and peripherals to take on their default

states, and the processor begins execution at address 0. When used as a port pin, P1.5

is a Schmitt trigger input only.

P1.6

DAC1 — Output from Digital to Analog Converter 1.

P1.7

DAC0 — Output from Digital to Analog Converter 0.

P2.0 - P2.1

7, 6

I/O

Port 2: Port 2 is a 2-bit I/O port with a user-conﬁgurable output type. Port 2 latches are

conﬁgured in the quasi-bidirectional mode and have either ones or zeros written to them

during reset, as determined by the PRHI bit in the UCFG1 conﬁguration byte. The

operation of port 2 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 8.9 “I/O ports” and

Table 55 “DC electrical characteristics” for details.

Port 2 also provides various special functions as described below:

P2.0

X2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is selected via

the EPROM conﬁguration.

CLKOUT — CPU clock divided by 6 clock output when enabled via SFR bit and in

conjunction with internal RC oscillator or external clock input.

P2.1

X1 — Input to the oscillator circuit and internal clock generator circuits (when selected

via the EPROM conﬁguration).

VSS

Ground: 0 V reference.

VDD

Power Supply: This is the power supply voltage for normal operation as well as Idle

and Power-down modes.

Table 2:

Pin description…continued

Symbol

Type

Description

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