ADP2311ACPZ-2-R7 datasheet(15/20 Pages) AD

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Data Sheet

ADP2311

Rev. B | Page 15 of 20

POWER FAIL COMPARATOR

The ADP2311 integrates a power fail comparator that can

generate a warning when the input voltage falls below the

designated voltage. When the PFI input voltage falls below

0.575 V, the PFO pin is pulled low. When the PFI input voltage

rises above 0.6 V, the PFO pin is pulled high. The low leakage

current of the PFI pin allows the use of a large value external

resistor to reduce system current consumption.

The PFO pin can be used to send a warning signal to the pro-

cessor in case of an abnormal input voltage condition so that

the processor can prepare to power down the system before

power is lost.

VOLTAGE MONITOR COMPARATOR (VM2)

The VM2 pin connects to an accurate comparator. When the

VM2 voltage falls below 0.6 V, Channel 2 is turned off. When

the VM2 voltage rises above 0.65 V, Channel 2 is allowed to

power up if the EN pin is high and PFI is above 0.6 V.

WATCHDOG TIMER

The watchdog timer circuit is used to monitor the activity of the

processor. During power-up, the watchdog timer circuit does not

acknowledge pulses from the WDI pin until the voltage at FB2 is

above the reset threshold and the reset timeout period (tRP) has

elapsed. During the power-up sequence, the RSTO pin is pulled

low and remains low until the watchdog timer circuit is activated.

The watchdog timer circuit can be initialized only by a low to

high transition on the WDI pin both after power up and after a

watchdog timeout (see Figure 36).

VOUT2

96.5%

tRP

tWD

tRP

WDI

RSTO

Figure 36. Watchdog Timing Diagram

After the watchdog timer circuit is active, it is cleared with every

low to high or high to low logic transition on the WDI pin, which

can detect pulse widths as short as 80 ns. If the WDI pin remains

high or low for longer than the watchdog timeout period (tWD),

a reset is asserted, and the RSTO pin is pulled low. The processor

is required to toggle the WDI pin within the timeout period;

therefore, it indicates a code execution error, and the generated

reset pulse (tRP) restarts the microprocessor in a known state.

The watchdog timer can also be cleared by a reset assertion due

to an undervoltage condition on VOUT2. When the FB2 voltage is

below the reset threshold, a reset is asserted; the watchdog timer

is cleared and does not begin counting again until reset is

deasserted.

The watchdog timeout (tWD) is set by the factory to one of four

possible values: 50 ms, 100 ms, 150 ms, and 200 ms (see the

Ordering Guide).

POWER-UP AND POWER-DOWN SEQUENCE

The ADP2311 has a controlled power-up and power-down

sequence. During power-up, Channel 1 is powered up before

Channel 2. During power-down, Channel 2 is powered down

before Channel 1.

Channel 1 does not power up until all of the following

conditions are met followed by a 128 cycle delay:

•

The PFI voltage exceeds 0.6 V.

•

The voltage on the EN pin exceeds 1.2 V.

•

Both the FB1 and FB2 voltages are less than 48 mV.

When VOUT1 reaches 96.5% of its normal voltage, Channel 2 is

powered up after a delay of 256 cycles.

During power-down, when the VM2 voltage falls below 0.6 V,

Channel 2 is turned off and power feedback occurs. Channel 2

energy is fed back to the input voltage to speed up the discharge

time of Channel 2. When the FB2 output voltage falls below

48 mV, Channel 1 is allowed to turn off, and power feedback

occurs to speed up the discharge time of Channel 1.

The power feedback feature allows the Channel 1 and Channel 2

output voltage fall time (100% to 10%) to be within 10 ms.

OVERVOLTAGE PROTECTION (OVP)

The ADP2311 provides an OVP feature to protect the system

against output shorts to a higher voltage supply or when a

strong load disconnect transient occurs.

If the feedback voltage increases to 0.7 V, the high-side MOSFET

turns off and the low-side MOSFET turns on until the negative

current limit threshold is triggered. After the negative current

limit threshold is triggered, both MOSFETs are held in the off

state until the FBx pin voltage falls to 0.63 V, at which point the

ADP2311 resumes normal operation.

UNDERVOLTAGE LOCKOUT (UVLO)

The UVLO threshold is 4.2 V with hysteresis of 0.5 V to prevent

power-on glitches on the device. When the PVIN1 or PVIN2

voltage rises above 4.2 V, Channel 1 or Channel 2 is enabled, and

the soft start period begins. When PVIN1 or PVIN2 falls below

3.7 V, Channel 1 or Channel 2 is turned off.

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