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SN74HCS367 Datenblatt(PDF) 10 Page - Texas Instruments |
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SN74HCS367 Datenblatt(HTML) 10 Page - Texas Instruments |
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10 / 30 page ![]() can be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations. Typically, a 10 kΩ resistor can be used to meet these requirements. Unused 3-state CMOS outputs should be left disconnected. 8.3.2 CMOS Schmitt-Trigger Inputs This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics table, using Ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers. 8.3.3 Clamp Diode Structure The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical Placement of Clamping Diodes for Each Input and Output. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. GND Logic Input Output VCC Device -IIK +IIK +IOK -IOK Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output 8.3.4 Wettable Flanks This device includes wettable flanks for at least one package. See the Features section on the front page of the data sheet for which packages include this feature. SN74HCS367-Q1 SCLS816A – SEPTEMBER 2020 – REVISED DECEMBER 2021 www.ti.com 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74HCS367-Q1 |
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