MAX1209 datasheet(12/27 Pages) MAXIM

12 / 27 page

12-Bit, 80Msps, 3.3V IF-Sampling ADC

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NAME

FUNCTION

REFP

Positive Reference I/O. The full-scale analog input range is

±(VREFP - VREFN). Bypass REFP to GND with

a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN.

Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side of the

printed circuit (PC) board.

REFN

Negative Reference I/O. The full-scale analog input range is

±(VREFP - VREFN). Bypass REFN to GND

with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and

REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side

of the PC board.

COM

Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to

GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the

opposite side of the PC board and connected to the MAX1209 through a via.

4, 7, 16,

GND

Ground. Connect all ground pins and EP together.

INP

Positive Analog Input

INN

Negative Analog Input

DCE

Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.

Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer.

CLKN

Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential

clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-

ended clock signal to CLKP and connect CLKN to GND.

CLKP

Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential

clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-

ended clock signal to CLKP and connect CLKN to GND.

CLKTYP

Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect

CLKTYP to OVDD or VDD to define the differential clock input.

12–15, 36

VDD

Analog Power Input. Connect VDD to a 3.0V to 3.6V power supply. Bypass VDD to GND with a parallel

capacitor combination of

≥2.2µF and 0.1µF. Connect all VDD pins to the same potential.

17, 34

OVDD

Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a

parallel capacitor combination of

≥2.2µF and 0.1µF.

DOR

Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of

range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog

input is within its full-scale range (Figure 6).

D11

CMOS Digital Output, Bit 11 (MSB)

D10

CMOS Digital Output, Bit 10

CMOS Digital Output, Bit 9

CMOS Digital Output, Bit 8

CMOS Digital Output, Bit 7

CMOS Digital Output, Bit 6

CMOS Digital Output, Bit 5

CMOS Digital Output, Bit 4

CMOS Digital Output, Bit 3

Pin Description

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