STM32WLE4JC datasheet(44/146 Pages) STMICROELECTRONICS

44 / 146 page

Functional overview

STM32WLE5/E4xx

44/146

DS13105 Rev 9

TIM16 and TIM17 main features:

•

general-purpose timers with mid-range features

•

16-bit auto-reload upcounters and 16-bit prescalers

•

1 channel and 1 complementary channel

•

channels that can all be used for input capture/output compare, PWM or one-pulse

mode output

•

counter that can be frozen in debug mode

•

independent DMA request generation

3.25.3

Low-power timers (LPTIM1, LPTIM2 and LPTIM3)

These low-power timers have an independent clock and run in Stop mode if they are

clocked by LSE, LSI, or by an external clock. They are able to wake up the system from

Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 and LPTIM3 are active in Stop 0 and Stop 1 modes.

LPTIM1/2/3 main features:

•

16-bit up counter with 16-bit autoreload register

•

16-bit compare register

•

configurable output: pulse, PWM

•

continuous/one-shot mode

•

selectable software/hardware input trigger

•

selectable clock source

•

internal clock sources: LSE, either LSI, HSI16 or APB clock

•

external clock source over LPTIM input (works even with no internal clock source

running, used by pulse counter application)

•

programmable digital glitch filter

•

encoder mode (LPTIM1 only)

3.25.4

Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and a 8-bit prescaler. The

IWDG is clocked from an independent 32 kHz internal RC (LSI). As the IWDG operates

independently from the main clock, it can operate in Stop and Standby modes.

The IWDG can be used either as a watchdog to reset the device when a problem occurs, or

as a free running timer for application timeout management. The IWDG is hardware or

software configurable through the option bytes. The counter can be frozen in debug mode.

3.25.5

System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. The

WWDG can be used as a watchdog to reset the device when a problem occurs.

The WWDG is clocked from the main clock and has an early warning interrupt capability.

The counter can be frozen in debug mode.

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