STM32WLE4JC datasheet(128/146 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32WLE5/E4xx

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DS13105 Rev 9

5.3.26

Communication interfaces characteristics

I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user

manual rev. 03 for:

•

Standard-mode (Sm): bitrate up to 100 Kbit/s

•

Fast-mode (Fm): bitrate up to 400 Kbit/s

•

Fast-mode Plus (Fm+): bitrate up to 1 Mbit/s

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly

configured (refer to the reference manual) and when the II2CCLK frequency is greater than

the minimum shown in the table below.

The SDA and SCL I/O requirements are met with the following restrictions:

•

The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,

the PMOS connected between the I/O pin and VDD is disabled, but is still present.

•

The 20 mA output drive requirement in Fast-mode Plus is partially supported. This

limits the maximum load Cload supported in Fast-mode Plus, given by these formulas:

–tr(SDA/SCL) = 0.8473 x Rp x Cload

–Rp(min) = [VDD - VOL(max)] / IOL(max)

where Rp is the I2C lines pull-up. Refer to Section 5.3.16: I/O port characteristics

for more details.

Table 88. IWDG min/max timeout period at 32 kHz (LSI)(1)

Prescaler divider

PR[2:0] bits

Min timeout (RL[11:0] = 0x000) Max timeout (RL[11:0] = 0xFFF) Unit

0x0

0.125

512

0x1

0.250

1024

/16

0x2

0.500

2048

/32

0x3

1.0

4096

/64

0x4

2.0

8192

/128

0x5

4.0

16384

/256

0x6 or 0x7

8.0

32768

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock, hence there is always a full

RC period of uncertainty.

Table 89. Minimum I2CCLK frequency in all I2C modes

Symbol

Parameter

Conditions

Min

Unit

f(I2CCLK)

I2CCLK frequency

Standard-mode

MHz

Fast-mode

Analog filter ON, DNF = 0

Analog filter OFF, DNF = 1

Fast-mode Plus

Analog filter ON, DNF = 0

Analog filter OFF, DNF = 1

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