VSC8540RT datasheet(34/87 Pages) MICROCHIP

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VSC8540RT

DS60001603E-page 34

 2022 Microchip Technology Inc. and its subsidiaries

When the EPG is enabled, packet loss occurs during transmission of packets from the MAC to the PHY. However, the

PHY receive output pins to the MAC are still active when the EPG is enabled. When it is necessary to disable the MAC

receive pins as well, set the register bit 0.10 to 1.

When the device register bit 29E1.14 is set to 1, the PHY begins transmitting Ethernet packets based on the settings in

registers 29E1 and 30E1. These registers set:

• Source and destination addresses for each packet

• Packet size

• Interpacket gap

• FCS state

• Transmit duration

• Payload pattern

When register bit 29E1.13 is set to 0, register bit 29E1.14 is cleared automatically after 30,000,000 packets are trans-

mitted.

5.17.2

FAR-END LOOPBACK

The far-end loopback testing feature is enabled by setting register bit 23.3 to 1. When enabled, it forces incoming data

from a link partner on the media interface into the MAC interface of the PHY where it is retransmitted back to the link

partner on the media interface, as shown in the following illustration. In addition, the incoming data also appears on the

receive data pins of the MAC interface. Data present on the transmit data pins of the MAC interface is ignored when

using this testing feature.

FIGURE 5-17:

FAR-END LOOPBACK DIAGRAM

5.17.3

NEAR-END LOOPBACK

When the near-end loopback testing feature is enabled, transmitted data (TXD) is looped back in the PCS block onto

the receive data signals (RXD), as shown in the following illustration. When using this testing feature, no data is trans-

mitted over the network. To enable near-end loopback, set the device register bit 0.14 to 1.

FIGURE 5-18:

NEAR-END LOOPBACK DIAGRAM

5.17.4

CONNECTOR LOOPBACK

The connector loopback testing feature allows the twisted pair interface to be looped back externally. When using this

feature, the PHY must be connected to a loopback connector or a loopback cable. Connect pair A to pair B, as shown

in the following illustration. The connector loopback feature functions at all available interface speeds.

FIGURE 5-19:

CONNECTOR LOOPBACK DIAGRAM

Link Partner

TXD

RXD

MAC

PHY_port_

Link Partner

TXD

RXD

MAC

PHY_port_

TXD

RXD

MAC

PHY_port_

Cat5

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