UCC28C53_V01 datasheet(18/48 Pages) TI

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input with a signal proportional to the error amplifier output voltage. The gain of the current sense amplifier is

typically 3 V/V. The peak ISENSE current is determined using Equation 2

SENSE

(2)

The typical value for VCS is 1 V. A small RC filter (RCSF and CCSF) may be required to suppress switch transients

caused by the reverse recovery of a secondary side diode or equivalent capacitive loading in addition to parasitic

circuit impedances. The time constant of this filter should be considerably less than the switching period of the

converter.

GND

COMP

2 R

CCSF

RCSF

RCS

PWM

Comparator

1 V

Error

Amplifier

ISENSE

Figure 8-3. Current-Sense Circuit Schematic

Cycle-by-cycle pulse width modulation performed at the PWM comparator essentially compares the error

amplifier output to the current sense input. This is not a direct volt-to-volt comparison, as the error amplifier

output network incorporates two diodes in series with a resistive divider network before connecting to the PWM

comparator. The two-diode drop adds an offset voltage that enables zero duty cycle to be achieved with a low

amplifier output. The 2R/R resistive divider facilitates the use of a wider error amplifier output swing that can be

more symmetrically centered on the 2.5-V noninverting input voltage.

The 1-V Zener diode associated with the PWM comparator input from the error amplifier is not an actual diode

in the device design, but an indication that the maximum current sense input amplitude is 1 V (typical). When

this threshold is reached, regardless of the error amplifier output voltage, cycle-by-cycle current limiting occurs,

and the output pulse width is terminated within 35 ns (typical). The minimum value for this current limit threshold

is 0.9 V with a 1.1-V maximum. In addition to the tolerance of this parameter, the accuracy of the current sense

resistor, or current sense circuitry, must be taken into account. It is advised to factor in the worst case of primary

and secondary currents when sizing the ratings and worst-case conditions in all power semiconductors and

magnetic components.

8.3.5 Reduced-Discharge Current Variation

The oscillator design for the UCCx8C5x controllers incorporates a trimmed discharge current to accurately

program maximum duty cycle and operating frequency. In its basic operation, a timing capacitor (CCT) is charged

by a current source, formed by the timing resistor (RRT) connected to the device reference voltage (VREF).

The oscillator design incorporates comparators to monitor the amplitude of the timing capacitor voltage. The

exponentially shaped waveform charges up to a specific amplitude representing the oscillator upper threshold of

3 V. After the controller reaches this level, an internal current sink to ground turns on and the capacitor begins

to discharge. This discharge continues until the oscillator lower threshold has reached 0.7 V at which point the

current sink is turned off. Next, the timing capacitor starts charging again and a new switching cycle begins.

UCC28C53, UCC28C54, UCC28C55

UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59

SLUSER8 – JUNE 2022

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