Data Sheet

ADL8106

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 7 of 26

Figure 2. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 3, 5, 6, 7, 9,

11, 12, 13, 14,

15, 17, 18, 19,

21, 22, 23, 24

GND

Ground. Connect to a ground plane that has low electrical and thermal impedance. See Figure 3 for the interface schematic.

4

RFIN

RF Input. The RFIN pin has a dc path to ground followed by an ac coupling capacitor in the RF signal path. If the dc bias level of the input

signal is not equal to 0 V, externally ac-couple the RFIN pin. See Figure 4 for the interface schematic.

8

VGG1

Negative Gate Bias Control. The gate voltage can be applied to VGG1. Adjust the negative voltage on the VGG1 pin to set the IDQ to the

desired level. See Figure 5 for the interface schematic.

10, 20

VDD1, VDD2

Drain Bias Pads with Integrated RF Chokes. Connect a common dc bias to the VDDx pads to provide drain current. See Figure 6 for the

interface schematic.

16

RFOUT

RF Output. The RFOUT pin has a resistive path to ground and an ac coupling capacitor in the RF signal path. If the dc bias level of the

next stage is not equal to 0 V, externally ac-couple the RFOUT pin. See Figure 6 for the interface schematic.

INTERFACE SCHEMATICS

Figure 3. GND Interface Schematic

Figure 4. RFIN Interface Schematic

Figure 5. VGG1 Interface Schematic

Figure 6. VDD1, VDD2, and RFOUT Interface Schematic