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AS1120

Data Sheet

Asynchronous Mode

Asynchronous Mode

Data can be preloaded into the AS1120 shift register and then activated via a LOAD pulse. To preload the shift register

the LOAD signal must stay high as all 46 data bits are clocked into the internal shift register at the rising edge of CLKIN

(see Figure 4).

Note: In asynchronous mode, a clock signal must be applied on pin BPLIN. Asynchronous mode does not support

the use of the AS1120 internal clock.

Figure 4. Timing Diagram for Preloading the Shift Register

To update the LCD display the LOAD signal must be held low for at least 8 periods of the clock applied at BPLIN, and

CLKIN must be set to low. Note that since BPLIN is normally asynchronous in respect to LOAD, it is advisable to keep

LOAD low for 8+1 BPLIN cycles. The display will be updated at the 8th BPLIN rising edge while LOAD is Low.

Figure 5. Timing Diagram for Updating the Display in Asynchronous Mode

R/C Oscillator and Backplane Generation

The AS1120 can generate the backplane signal using an internal R/C oscillator, or an externally generated backplane

signal can be supplied.

When cascading multiple AS1120 devices (see Figure 7 on page 8), only the first device should have the oscillator run-

ning; the other devices must use pin BPLIN to regenerate the backplane signal and to synchronize their LCD output

segments with the common backplane.

BPLIN

CLKIN

Stop

DATAIN

X

X LD45 LD45LD45

LD0

LD1

LD2

LD3

LD4

LD5

LD6

LD7

LD8

LD9

LD10

LOAD Always High

LOAD

46 CLKIN Cycles

9 BPLIN Cycles

LOAD

CLKIN

DATAIN

X

XX

X

X

X

X

X

X

X

X

X

X

X

CLKIN Always High

XX

X

BPLIN

Display

Update