HMN1M8DN datasheet(5/9 Pages) HANBIT

5 / 9 page

HANBit

HMN1M8DN

URL : www.hbe.co.kr

HANBit Electronics Co.,Ltd.

REV. 0.2 (August, 2002)

READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax )

-70

-85

-120

-150

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Read Cycle Time

tRC

120

150

Address Access Time

tACC

Output load A

120

150

Chip enable access time

tACE

Output load A

120

150

Output enable to Output valid

tOE

Output load A

Chip enable to output in low Z

tCLZ

Output load B

Output enable to output in low Z

tOLZ

Output load B

Chip disable to output in high Z

tCHZ

Output load B

Output disable to output high Z

tOHZ

Output load B

Output hold from address change

tOH

Output load A

WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax )

-70

-85

-120

-150

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

Min

Max

UNI

Write Cycle Time

tWC

120

150

Chip enable to end of write

tCW

Note 1

100

Address setup time

tAS

Note 2

Address valid to end of write

tAW

Note 1

100

Write pulse width

tWP

Note 1

Write recovery time (write cycle 1)

tWR1

Note 3

Write recovery time (write cycle 2)

tWR2

Note 3

Data valid to end of write

tDW

Data hold time (write cycle 1)

tDH1

Note 4

Data hold time (write cycle 2)

tDH2

Note 4

Write enabled to output in high Z

tWZ

Note 5

Output active from end of write

tOW

Note 5

NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.

2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE

going low and /WE going low.

3. Either tWR1 or tWR2 must be met.

4. Either tDH1 or tDH2 must be met.

5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-

impedance state.

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