©2012 Silicon Storage Technology, Inc.

DS25023B

06/13

16

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Figure 8: Toggle Bit Timing Diagram

Figure 9: WE# Controlled Sector-Erase Timing Diagram

1150 F07.0

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note:

AMS = Most significant address

AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040

1150 F08.0

ADDRESS AMS-0

DQ7-0

WE#

SW0

SW1

SW2

SW3

SW4

SW5

5555

2AAA

2AAA

5555

5555

55

30

55

AA

80

AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minmum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040