AT25DF641A datasheet(39/57 Pages) RENESAS

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AT25DF641A [DATASHEET]

8793G–DFLASH–02/2022

11.2 Write Status Register Byte 1

The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Register and/or to perform a

Global Protect or Global Unprotect operation. Before the Write Status Register Byte 1 command can be issued, the Write

Enable command must have been previously issued to set the WEL bit in the Status Register to a Logical 1.

To issue the Write Status Register Byte 1 command, the CS pin must first be asserted and the opcode of 01h must be

clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a dummy bit,

four data bits to denote whether a Global Protect or Unprotect should be performed, and two additional dummy bits (see

Table 11-3). Any additional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the

SPRL bit in the Status Register will be modified, and the WEL bit in the Status Register will be reset back to a

Logical 0. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before the Write Status Register Byte 1

command was executed (the prior state of the SPRL bit) will determine whether or not a Global Protect or Global

Unprotect will be performed. See “Global Protect/Unprotect” on page 25 for more details.

The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of

the SPRL bit will not change, no potential Global Protect or Unprotect will be performed, and the WEL bit in the Status

If the WP pin is asserted, then the SPRL bit can only be set to a Logical 1. If an attempt is made to reset the SPRL bit to

a Logical 0 while the WP pin is asserted, then the Write Status Register Byte 1 command will be ignored, and the WEL bit

in the Status Register will be reset back to the Logical 0 state. In order to reset the SPRL bit to a Logical 0, the WP pin

must be deasserted.

Table 11-3. Write Status Register Byte 1 Format

Figure 11-2. Write Status Register Byte 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPRL

Global Protect/Unprotect

SCK

MSB

0000000

Opcode

10 11

814 15

MSB

DXD

Status Register In

Byte 1

High-impedance

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