AT25SL128A datasheet(7/84 Pages) RENESAS

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DS-AT25SL128A-109 Rev. R

Page 7

Sep 14, 2022

AT25SL128A Datasheet

Introduction

The AT25SL128A is a serial interface Flash memory device designed for use in a wide variety of high-volume

consumer based applications in which program code is shadowed from Flash memory into embedded or external

RAM for execution. The flexible erase architecture of the AT25SL128A is ideal for data storage as well, eliminating

the need for additional data storage devices.

The erase block sizes of the AT25SL128A have been optimized to meet the needs of today's code and data

storage applications. By optimizing the size of the erase blocks, the memory space can be used much more

efficiently. Because certain code modules and data storage segments must reside by themselves in their own

erase regions, the wasted and unused memory space that occurs with large block erase Flash memory devices

can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage

segments to be added while still maintaining the same overall device density.

SPI clock frequencies of up to 133 MHz are supported, allowing equivalent clock rates of 266 MHz for Dual

Output, and 532 MHz for Quad Output when using the QPI and Fast Read Dual/Quad I/O commands.The

AT25SL128A array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be

programmed at a time using the Page Program commands. Pages can be erased in block increments of 4 kbytes,

32 kbytes, or 64 kbytes, or the entire chip.

The devices operate on a single 1.7 V to 2.0 V power supply with current consumption as low as 5 mA active and

2 µA for Deep Power Down. All devices offered in space-saving packages. The device supports JEDEC standard

manufacturer and device identification with a 4-kbit secured OTP.

The physical block size for this device is 8 Mbit.

AT25SL128A Datenblatt(PDF) 7 Page - Renesas Technology Corp