HIP6200, HIP6201

FN4423 Rev 3.00

Page 6 of 9

February 5, 2015

Detailed Functional Description

As shown in the Block Diagram, the HIP6200 has two

comparators which compare the voltage on the CAP pin to

the voltage on the SNS pin. The CAP voltage follows the

SNS voltage with an R-C delay which is user programmable

and also variable depending upon the state of the amplifiers.

Normally, resistor RT1 is in parallel with RT2 when the

amplifiers are not active. RT1 is small and the CAP voltage

(VCAP) follows the SNS voltage (VSNS) closely. During a

transient, when either amplifier is active, the switch in series

with RT1 opens and RT2 alone (with the capacitor on CAP)

sets the time constant. Since RT2 is 20 times larger than

RT1, the DeCAPitator has time to source or sink current as

the inductor current slews. The CAP voltage waveform is

depicted in the Typical Application Diagrams.

Prior to the load transient, VCAP follows VOUT (and

likewise VSNS) closely. This is important in many portable

applications because the DC/DC converter will be in an

energy-saving skip-cycle mode at light load currents. In this

mode, the output voltage ripple may be in excess of

2%

and could trip the HIP6200’s comparators if VCAP did not

track VSNS. This would turn on the amplifiers and waste

power. When a fast load transient occurs, VCAP no longer

follows VOUT and the DeCAPitator becomes active when

VOUT exceeds +1% or -1.5% of VCAP.

When the DeCAPitator is active, it either supplies current

from the PVCC pin or sources current to PGND. Because of

this, a high-quality capacitor must be placed locally from

PVCC to GND. The system 5V bus typically has a good

deal of bulk capacitance as well as high frequency

decoupling sprinkled across the application board. PVCC is

tied to the system 5V bus through an on-chip 10

 resistor.

This resistor helps isolate the system 5V from the

disturbances on PVCC.

The HIP6200 has a power-on reset function which ensures

that both VCC and CAP are at some minimum levels before

allowing amplifier operation. There is also an EN(ABLE) pin,

allowing users to disable the HIP6200 if desired. An

overtemperature (OT) shutdown feature ensures that the

HIP6200 will not self-destruct from thermal overload. An OT

event will shutdown the chip until the junction temperature

decreases a few degrees below its trip point.

The DeCAPitator draws very little bias current (300

A

typical) when its amplifiers are inactive. When either

amplifier is active, the chip draws 15-30mA of bias current.

This current is mainly for the active high-speed amplifier and

lasts only for the duration of the on-time of the HIP6200.

Component Selection Guidelines

Bulk Output Capacitors

For a given converter design without the HIP6200 in the

target application, the number of output capacitors is

determined mainly by the output voltage regulation and

transient specifications. It is estimated that for a load

transient of 0-8A with a di/dt of 20A/

s, eleven 220F, 0.1

low ESR tantalum capacitors are necessary to maintain CPU

core voltage regulation specifications. For identical

conditions with a HIP6200 employed, only five 100

F, 0.1

low ESR tantalums are required. Similar savings in output

capacitance can be achieved with other capacitor dielectric-

types.

The number of capacitors which can be eliminated on the

output is limited by either of the following:

1. Output voltage ripple - this increases proportional to the

equivalent ESR of the bulk output capacitance. This may

be counteracted by increasing the output inductance. In

many cases the inductor can remain the same because

the output ripple will still be acceptably small.

2. Leading edge voltage spike - this may increase with re-

duced number of capacitors. The HIP6200 and its very

fast response is very effective in handling this leading

edge spike up to a point. Some additional ceramic decou-

pling on the OUT pin can also help.

PVCC Capacitor

A 100

F, 0.1tantalum is recommended on the PVCC pin

for an application which has 8A transients (maximum

recommended operation of the HIP6200). RVCC is an

internal 10

 resistor from VCC to PVCC which decouples the

PVCC transient from the system 5V (VCC).

CAP Capacitor

The capacitor on the CAP pin sets the amount of time that

the HIP6200 has to sink or source current in response to a

load transient. The DeCAPitator on-time should be greater

than the converter response time. When the HIP6200’s

amplifiers are not active, the CAP pin follows the output

voltage closely to prevent false tripping at light loads due to

PWM skip-cycle modes of operation. These two boundaries

are addressed with RT1 and RT2 internal to the HIP6200

but must also be verified on each design.

The converter response time is the time interval required for

the inductor current to slew to the output load current. This

time is dramatically different for the two edges of the

transient event if there is a large differential between input

and output voltages of the converter. The converter

response times are approximated by v = L*di/dt:

where

TR1 = converter response time to low-to-high load transient

TR2 = converter response time to high-to-low load transient

TR1 LOUT

ISTEP

VIN VOUT

–



-------------------------------------



=

(EQ. 1)

TR2 LOUT

ISTEP

VOUT



---------------------



=

(EQ. 2)