HIP6200, HIP6201

FN4423 Rev 3.00

Page 9 of 9

February 5, 2015

Layout Considerations

FIGURE 6. TYPICAL SCHEMATIC

CAP

VCC

PVCC

OUT

GND

EN

SNS

PGND

P5V

C39

C38

0.1



C37

100



10V

C24-26

3x

1



16V

+

RTN

VOUT

4

8

5

3

2

6

7

1

8200p

RTN

C19-23

5x

100



10V

+

CERAMIC DECOUPLING

FOR HIGH di/dt LOAD

(MAY NOT BE REQUIRED)

BULK OUTPUT CAPACITANCE

OF DC/DC CONVERTER

OUTPUT OF DC/DC

(OUTPUT INDUCTOR)

FROM

P CORE

HIP6201

U3

Example Layout

• HIP6200 located near bulk output capacitance (not shown is the microprocessor load itself - for best performance, the

HIP6200 and bulk output capacitance should be located close to the

P)

•C37 (+5V bulk cap) located near the HIP6200

• Solid ground and VOUT planes with numerous via interconnects

TOP - SILK SCREEN

TOP - COMPONENT SIDE

SOLDER SIDE

INTERNAL ONE

NOTE: Internal layers are shown as negatives

(white is copper):

via connection to copper plane

no connection

GND