APR3SLASHD datasheet(26/101 Pages) NXP

26 / 101 page

2-8

DSP56001A/D, Rev. 1

MOTOROLA

DSP56001A

RESET, Stop, Mode Select, and Interrupt Timing

17 Delay from IRQA, IRQB

Assertion to External Memory

Access Address Out Valid

•

Caused by First

Interrupt Instruction

Fetch

•

Caused by First

Interrupt Instruction

Execution

× T

C + TH

× T

C + TH

—

× T

C + TH

× T

C + TH

—

18 Delay from IRQA, IRQB

Assertion to General Purpose

Transfer Output Valid caused

by First Interrupt Instruction

Execution

× T

C + TH

—

× T

C + TH

—ns

19 Delay from Address Output

Valid caused by First Interrupt

Instruction Execute to Interrupt

Request Deassertion for Level-

Sensitive Fast Interrupts (See

Note 3)

—2

× T

C + TL +

(TC × WS) –

—2

× T

C + TL +

(TC × WS) –

20 Delay from RD Assertion to

Interrupt Request Deassertion

for Level-Sensitive Fast

Interrupts (See Note 3)

—2

× T

C +

(TC × WS) –

—2

× T

C +

(TC × WS) –

21 Delay from WR Assertion to

Interrupt Request Deassertion

for Level-Sensitive Fast

Interrupts (See Note 3)

•

WS = 0

•

WS > 0

—

× T

C – 31

TC + TL +

(TC × WS) –

—

× T

C – 25

TC + TL +

(TC × WS) –

Table 2-8

Reset, Stop, Mode Select, and Interrupt Timing (27/33 MHz) (Continued)

Num

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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