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November 16, 2007

IDT70P9268

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM

Industrial Temperature Range

Pin Configuration

IDT70P9268

BY100

100-BALL fpBGA

NOTES:

1. The device setup shown above features multiplexed address and data signals on the right port and non-multiplexed address and data signals on the left port.

2. For multiplexed address and data signal operation on the left port, this pin should be set to VDD. For non-multiplexed address and data signal operation on the left port,

this pin should be set to VSS.

3. For multiplexed address and data signal operation on the left port, these pins should be set to VSS.

A1

VSS

A2

I/O0R

A3

VDD

A4

I/O4R

A5

I/O7R

A6

VDD

A7

I/O10R

A8

VDD

A9

I/O15R

A10

SFEN

B1

R/

WR

B2

CLKR

B3

I/O1R

B4

VSS

B5

I/O5R

B6

VSS

B7

I/O11R

B8

VSS

B9

I/O14R

B10

OER

C1

ADSR

C2

CNTENR

C3

CNTRPTR

C4

I/O2R

C5

I/O6R

C6

I/O8R

C7

I/O12R

C8

ZZR

C9

SF7

C10

VSS

D1

CER

D2

INTR

D3

UBR

D4

LBR

D5

I/O3R

D6

I/O9R

D7

I/O13R

D8

SF6

D9

SF5

D10

SF4

E1

INTL

E2

VSS

E3

VDD

E4

UBL

E5

CNTRPTL

E6

SF0

E7

MSEL(2)

E8

VDD

E9

VSS

E10

VDD

F1

CEL

F2

LBL

F3

CNTENL

F4

CLKL

F5

VSS

F6

A13L(3)

F7

SF2

F8

VSS

F9

VSS

F10

SF1

G1

ADSL

G2

A0L(3)

G3

A3L(3)

G4

VDD

G5

I/O8L

G6

I/O12L

G7

A7L(3)

G8

ZZL

G9

OEL

G10

SF3

H1

R/

WL

H2

A2L(3)

H3

I/O0L

H4

VSS

H5

I/O4L

H6

I/O11L

H7

I/O13L

H8

A9L(3)

H9

A12L(3)

H10

NC

J1

A1L(3)

J2

A5L(3)

J3

I/O1L

J4

I/O6L

J5

I/O7L

J6

I/O9L

J7

VDD

J8

I/O15L

J9

A10L(3)

J10

A11L(3)

K1

A4L(3)

K2

A6L(3)

K3

I/O2L

K4

I/O3L

K5

I/O5L

K6

VDD

K7

I/O10L

K8

VSS

K9

I/O14L

K10

A8L(3)