ICS87004AG REVISION C DECEMBER 1, 2009

6

©2009 Integrated Device Technology, Inc.

ICS87004 Data Sheet

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C

NOTE 1: Outputs terminated with 50

Ω to V

DDO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams.

Table 4D. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C

NOTE 1: VIL should not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as VIH.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

VIH

Input High Voltage

VDD = 3.3V

2

VDD + 0.3

V

VDD = 2.5V

1.7

VDD + 0.3

V

VIL

Input Low Voltage

VDD = 3.3V

-0.3

0.8

V

VDD = 2.5V

-0.3

0.7

V

IIH

Input High Current

SEL[0:3], MR,

FB_IN, CLK_SEL

VDD = VIN = 3.465V or 2.625V

150

µA

PLL_SEL

VDD = VIN = 3.465V or 2.625V

5

µA

IIL

Input Low Current

SEL[0:3], MR,

FB_IN, CLK_SEL

VDD = 3.465V or 2.625V,

VIN = 0V

-5

µA

PLL_SEL

VDD = 3.465V or 2.625V,

VIN = 0V

-150

µA

VOH

Output High Voltage; NOTE 1

VDDO = 3.465V

2.6

V

VDDO = 2.625V

1.8

V

VOL

Output Low Voltage; NOTE 1

VDD = 3.465V or 2.625V

0.5

V

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

IIH

Input

High Current

CLK0/nCLK0,

CLK1/nCLK1

VDD = VIN = 3.465V or 2.625V

150

µA

IIL

Input

Low Current

CLK0, CLK1

VDD = 3.465V or 2.625V, VIN = 0V

-5

µA

nCLK0, nCLK1

VDD = 3.465V or 2.625V, VIN = 0V

-150

µA

VPP

Peak-to-Peak Voltage; NOTE 1

0.15

1.3

V

VCMR

Common Mode Input Voltage;

NOTE 1, 2

GND + 0.5

VDD – 0.85

V