ICS87004AG REVISION C DECEMBER 1, 2009

7

©2009 Integrated Device Technology, Inc.

ICS87004 Data Sheet

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

AC Electrical Characteristics

Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.

NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and

the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.

NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and

the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

15.625

250

MHz

tPD

Propagation Delay;

NOTE 1

CLK0, nCLK0

CLK1, nCLK1

PLL_SEL = 0V, f

≤ 250MHz,

Qx ÷ 2

56.2

ns

t(Ø)

Static Phase Offset;

NOTE 2, 4

CLK0, nCLK0

PLL_SEL = 3.3V,

fREF ≤ 167MHz, Qx ÷ 1

-75

50

175

ps

CLK1, nCLK1

-190

-65

175

ps

tsk(o)

Output Skew;

NOTE 3, 4

CLK0, nCLK0

CLK1, nCLK1

PLL_SEL = 0V

40

50

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 4

fOUT > 40MHz

30

45

ps

tL

PLL Lock Time

1ms

tR / tF

Output Rise/Fall Time

20% to 80%

400

800

ps

odc

Output Duty Cycle

40

50

60

%

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

15.625

250

MHz

tPD

Propagation Delay;

NOTE 1

CLK0, nCLK0

CLK1, nCLK1

PLL_SEL = 0V, f

≤ 250MHz,

Qx ÷ 2

5.3

6.9

ns

t(Ø)

Static Phase Offset;

NOTE 2, 4

CLK0, nCLK0

PLL_SEL = 2.5V,

fREF ≤ 167MHz, Qx ÷ 1

-175

-25

125

ps

CLK1, nCLK1

-290

-115

125

ps

tsk(o)

Output Skew;

NOTE 3, 4

CLK0, nCLK0

CLK1, nCLK1

PLL_SEL = 0V

40

45

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 4

fOUT > 40MHz

35

45

ps

tL

PLL Lock Time

1ms

tR / tF

Output Rise/Fall Time

20% to 80%

400

700

ps

odc

Output Duty Cycle

44

50

56

%