LTC4260IGN datasheet(15/28 Pages) LINER

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LTC4260

4260f

Gate Pin Voltage

A curve of gate drive vs VDD is shown in the Typical

Performance curves. At the minimum input supply volt-

age of 8.5V, the minimum gate drive voltage is 4.5V.

When the input supply voltage is higher than 20V, the gate

drive is at least 10V and a regular N-FET can be used. In

applications over a 8.5V to 20V range, a logic level N-FET

must be used to maintain adequate gate enhancement.

The GATE pin is clamped at a typical value of 15V above

the SOURCE pin.

Configuring the GPIO Pin

Table 3 describes the possible states of the GPIO pin using

the control register bits A6 and A7. At power-up, the

default state is for the GPIO pin to go high impedance when

power is good (FB pin greater than 3.5V). Other uses for

the GPIO pin are to pull down when power is good, a

general purpose output and a general purpose input.

Compensating the Active Current Loop

The active current limit circuit is compensated using the

resistor R6 and the slew rate capacitor C1. The value for C1

is calculated to limit the inrush current. The suggested

value for R6 is 100k. This value should work for most pass

FETs (Q1). If the gate capacitance of Q1 is very small then

the best method to compensate the loop is to add a ≈10nF

capacitor between the GATE and SOURCE terminals.

Supply Transients

The LTC4260 is designed to ride through supply transients

caused by load steps. If there is a shorted load and the

parasitic inductance back to the supply is greater than

0.5µH, there is a chance that the supply could collapse

before the active current limit circuit brings down the

GATE pin. In this case the undervoltage monitors turn off

the pass FET. The undervoltage lockout circuit has a 5µs

filter time after VDD drops below 7.5V. The UV pin reacts

in 2µs to shut the GATE off, but it is recommended to add

a filter capacitor CF to prevent unwanted shutdown caused

by short transient. Eventually either the UV pin or the

undervoltage lockout responds to bring the current under

control before the supply completely collapses.

Supply Transient Protection

The LTC4260 is 100% tested and guaranteed to be safe

from damage with supply voltages up to 100V. However,

spikes above 100V may damage the part. During a short-

circuit condition, the large change in currents flowing

through the power supply traces can cause inductive

voltage spikes which could exceed 100V. To minimize the

spikes, the power trace inductance should be minimized

by using wider traces or heavier trace plating. Adding a

snubber circuit will dampen the voltage spikes. It is built

using a 100Ω resistor in series with a 0.1µF capacitor

between VDD and GND. A surge suppressor, Z1 in Figure 1,

at the input will clamp the voltage spikes.

Design Example

As a design example, take the following specifications: VIN

= 48V, IMAX = 5A, IINRUSH = 1A, CL= 330µF, VUVON = 43V,

VUVOFF= 38.5V, VOVOFF= 70V, VPWRGDUP= 46V, VPWRGDDN

= 45V and I2CADDRESS = 1010011. The selection of the

sense resistor, RS, is set by the overcurrent threshold of

50mV:

MAX

===

Ω

0 010

The FET should be sized to handle the power dissipation

during the inrush charging of the output capacitor COUT.

The method used to determine the power is the principle:

EC = Energy in CL= Energy in Q1

Thus:

EC = 1/2 CV2 = 1/2(0.33mF)(48V)2 = 0.38J

Calculate the time it takes to charge up COUT:

CHARGUP

LIN

INRUSH

••

330

The average power dissipated in the FET:

DISS

CHARGUP

≅

038

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