Nexperia

74HC166; 74HCT166

8-bit parallel-in/serial out shift register

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care; ↑ = LOW-to-HIGH clock transition.

Inputs

Qn registers

Output

Operating modes

PE

CE

CP

DS

D0 to D7

Q0

Q1 to Q6

Q7

I

I

↑

X

I

L

L to L

L

parallel load

I

I

↑

X

h

H

H to H

H

h

I

↑

l

X

L

q0 to q5

q6

serial shift

h

I

↑

h

X

H

q0 to q5

q6

hold "do nothing"

X

H

X

X

X

q0

q1 to q6

q7

H

L

H

L

H

L

H

H

load

aaa-008820

clear

CP

MR

DS

shift/

load

D0

D1

D2

D3

D4

D5

D6

D7

Q7

CE

mode

control

inputs

parallel

inputs

output

inhibit

serial shift

serial shift

H H L

H

H

H

L

L

Fig. 7. Typical clear, shift, load, inhibit, and shift sequences

74HC_HCT166

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 5 — 9 August 2021

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