Nexperia

74LVC594A

8-bit shift register with output register

-40 °C to +85 °C

-40 °C to +125 °C

Symbol Parameter

Conditions

Min

Typ[1]

Max

Min

Max

Unit

tsk(o)

output skew time VCC = 3.0 V to 3.6 V

[4]

-

-

1.0

-

1.5

ns

VI = GND to VCC

[5]

VCC = 1.65 V to 1.95 V

-

50

-

-

-

pF

VCC = 2.3 V to 2.7 V

-

45

-

-

-

pF

CPD

power dissipation

capacitance

VCC = 3.0 V to 3.6 V

-

44

-

-

-

pF

[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] tpd is the same as tPLH and tPHL.

[3] Cascadability is guaranteed under identical VCC and temperature conditions.

[4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[5] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD x VCC 2 x fi x N + ∑(CL x VCC 2 x fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL x VCC 2 x fo) = sum of outputs.

11.1. Waveforms and test circuit

mna557

SHCP input

Q7S output

tPLH

tPHL

tW

1/fmax

VM

VOH

VI

GND

VOL

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and

maximum shift clock frequency

74LVC594A

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Product data sheet

Rev. 4 — 3 September 2020

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