Nexperia

74LVC594A

8-bit shift register with output register

mbc326

VM

tsu

VM

VM

STCP input

Qn outputs

SHR input

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 10. The shift reset (SHR) to storage clock (STCP) set-up times

mbc324

VM

tPHL

VM

trec

tW

VM

SHCP input

Q7S output

SHR input

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 11. The shift reset (SHR) pulse width, the shift reset to serial data output (Q7S) propagation delays and the

shift reset to shift clock (SHCP) recovery time

mbc325

VM

tPHL

VM

trec

tW

VM

STCP input

Qn outputs

STR input

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 12. The storage reset (STR) pulse width, the storage reset to parallel data output (Qn) propagation delays and

the storage reset to storage clock (STCP) recovery time

74LVC594A

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© Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 4 — 3 September 2020

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