11

VP7615

Address 0x0C Output Sense Control Register

Read/Write

Bit 7

SWPYUV - YY and UV Swap

‘0’ =

Normal: YY and UV are in proper positions

CCIR601 output mode: YY data on YY bus; UV data on UV bus CCIR656

output mode: UYVY

‘1’ =

Swapped: YY and UV in each other’s positions

CCIR601 output mode: UV data on YY bus; YY data on UV bus CCIR656

output mode: YUYV .

Bit 6

SWPUV - UV Swap

‘0’ =

Normal: U and V are in position for CCIR601/656: U before V

‘1’ =

Swapped: U and V are swapped in time: V before U

Bit 5

VAG - VACT Gate

‘1’ =

Gated: VACT active gated by HACT

‘0’ =

Normal: VACT active during Active Lines

Bit 4

HAG - HACT Gate

‘1’ =

Gated: HACT active gated by VACT

‘0’ =

Normal: HACT active during Active Pixels

Bit 3

VAS - VACT Sense

‘1’ =

Active High: VACT = 1 during Active Lines

‘0’ =

Active Low: VACT = 0 during Active Lines

Bit 2

HAS - HACT Sense

‘1’ =

Active High: HACT = 1 during Active Pixels

‘0’ =

Active Low: HACT = 0 during Active Pixels

Bit 1

VSS - VSYNC Sense

‘1’ =

Active High: VSYNC = 1 during Vertical Sync

‘0’ =

Active Low: VSYNC = 0 during Vertical Sync

Bit 0

HSS - HSYNC Sense

‘1’ =

Active High: HSYNC = 1 during Horizontal Sync

‘0’ =

Active Low: HSYNC = 0 during Horizontal Sync

This register defaults on chip reset to 0x0C.

Address 0x0D VACT Control Register

Read/Write

Bit 7

VAFIX - VACT Control

This bit provides backward compatibility for certain iCam cameras.

‘0’ =

Disabled:

VACT controlled by camera timing

‘1’ =

Enabled:

VACT is inactive during a fixed number of lines during Vertical Blanking.

This only effects the end, and not the beginning, of Vertical Blanking.

Bit 6

Always read as ‘0’

Bits 5 - 0

VFCnt5 - VFCnt0

This field modifies the end of Vertical Blanking if VAFIX is ‘1’ by setting the number of lines that

VACT will be inactive during Vertical Blanking.

This register defaults on chip reset to 0x3F.

7

SWPYUV

6

SWPUV

5

VAG

4

HAG

3

VAS

2

HAS

1

VSS

0

HSS

7

VAFIX

6

0

5

VFCnt5

4

VFCnt4

3

VFCnt3

2

VFCnt2

1

VFCnt1

0

VFCnt0