VP7615 datasheet(16/25 Pages) MITEL

16 / 25 page

VP7615

Fig.2 Video Interface Timing Diagram

CPCKA

or CPCKB

CLK1

VSYNC, HSYNC

VACT, HACT

BFLAG, FIELD

VSYNC, HSYNC

VACT, HACT

BFLAG, FIELD

YY[7:0]

UV[7:0]

CCSEL = Low

YY[7:0]

CCSEL = High

CPCKA

or CPCKB

CLK2

CLK1

tcpCK1f

tcqCPX

tpdCK2

tcqCPX

tcpCK2f

LUMA

CHROMA

LUMA

CHROMA

OUTEN

CLK1, CLK2

VSYNC, HSYNC,

VACT, HACT

BFLAG, FIELD

YY[7:0], UV[7:0]

toen

tdis

High Impedance

Signal Timing

The clock source for the VP7615 is the clock input of the

selected CamPort. Since there are two CamPort inputs, the

selected clock is brought out as an output, namely CLK2.

Since the frequency of this clock is twice the pixel rate, another

output, CLK1, is provided which runs at the pixel rate.

It is anticipated that the VP7615 user would use one or both of

these clocks to clock the data and timing outputs into another

device. In order to assure hold times into any device, the clock

outputs CLK1 and CLK2 were inverted inside the VP7615 so

that the data and timing outputs would change near the falling

edge of these clocks, and would be stable at their rising edges.

The timing specifications characterize the delay from the

falling edges of CLK1 and CLK2 to the edges of the data and

timing outputs. It is left to the system designer to calculate the

available setup and hold times based on these timing

specifications, the period of CLK1 and CLK2 and their duty

cycles.

VP7615 Datenblatt(PDF) 16 Page - Mitel Networks Corporation

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